1. Field of the Invention
The present invention relates generally to logic storage element circuits and more particularly to storage circuits utilizing field effect transistors.
2. Description of the Prior Art
Static storage element circuits comprising complementary channel MIS field effect transistors (FETs) are shown and described in the publication ISSCC 74/February 15, High-Density ESFI MOS Memory Cells. K. Goser. These are:
A. FIVE TRANSISTOR CIRCUITS WITH FOUR SUPPLY LINES AND A LARGE AREA REQUIREMENT HAVING RAPID SWITCHING FROM ONE LOGIC STATE INTO THE OTHER;
B. THREE TRANSISTOR CIRCUITS WITH FOUR SUPPLY LINES WHICH CAN BE SWITCHED RELATIVELY SLOWLY FROM ONE LOGIC STATE INTO THE OTHER DUE TO THE USE OF HIGH OHMIC LOAD RESISTORS;
C. Two transistor circuits with a diode and three supply lines which also switch relatively slowly from one logic state into the other since high ohmic load elements are employed.
Thus there are circuits which have a small area requirement but which switch slowly from one logic state into the other. Also, there are circuits which can be switched rapidly from one logic state into the other, but also require a large area space.